1. Technical Field
This invention relates to digital signal busses, and more particularly to signal bus interface circuitry.
2. Background Art
The cockpit instrumentation of modern day commercial aircraft has become increasingly complex with the need for functional integration of the flight systems equipment. This requires communications between cockpit instruments, radios and navigational display devices. Specifically, the navigation and communication radios (NAVCOM""s) exchange signal information with other cockpit instruments over a digital signal bus standard known as the Commercial Standard Digital Bus (CSDB). The CSDB is functionally defined by the Collins Corporation Standard 523-0772774.
Aircraft flight control computers, such as the Aircraft System Computer (ASC) designed by the Hamilton Standard Division of United Technologies Corporation for the Sikorsky Aircraft Corporation commercial Model S92 helicopter, must also communicate with each of the aircraft""s various instruments and sensors, including the NAVCOM""s. The ASC receives sensor data through the CSDB and presents flight data information on the CSDB to the cockpit displays. This requires translation of signal protocols between the ASC and the CSDB.
Although certain other aircraft signal buses, such as the military standard for digital signal buses (MIL-STD 1553) and the avionics bus standard (ARINC 429), have commercially available interface devices for translating protocols among the different bus connected equipment, no such similar interface device exists for the CSDB. While it is possible to incorporate a microcontroller or microprocessor-based solution to provide this interface, the high costs of the required microprocessor components and the software make this an expensive solution.
One object of the present invention is to provide a full feature CSDB interface in hardware-based circuitry capable of receiving CSDB protocol data frames from several different signal sources.
According to the present invention, interface apparatus is adapted for interconnection between a host computer and the CSDB for receiving data frames from different identified signal sources in CSDB format, translating the received CSDB signal protocol into a form compatible with the host computer, and storing the translated messages in signal memory which is accessible to the host processor. In further accord with the invention, the memory is segregated into groups of addressable locations, each group being assigned to receive the translated protocol data signals from a different one of the identified signal sources.
In still further accord with the invention, different sub-groups of addressable memory locations are designated within each parent address group for receiving and storing therein the translated protocol data signals from a common signal source, but having different subject content. In still yet further accord with the present invention each of the sub-groups have a designated primary and secondary address location to which succeeding units of the translated protocol signal data is stored by the interface and retrieved by the host computer, in ordered, cyclic fashion, thereby providing for a fast and efficient transfer of the translated data to the host computer.
The CSDB interface of the present invention is a hardware based interface capable of translating the CSDB protocol encoded data from a number of different signal sources, at high transfer rates, to a format acceptable to the host computer. The interface notifies the host of the receipt of each CSDB data frame, as well as the storing of each message of the frame, and the host acknowledges its retrieval of each stored message. As a result the messages are transferred in a synchronized manner to preserve data coherency and without loss of bit content.
Within the interface apparatus, the synchronization of store and retrieve is established by address generation logic circuitry in conjunction with ping-pong buffer logic (PPBL) and memory arbitration logic (MAL). By double buffering incoming messages the PPBL ensures data coherency; i.e. that all data bytes within a message block come from the same transmission,. The PPBL coordinates the double buffering with the host computer to provide this data coherency. The final product of the interface apparatus is a plurality of presorted messages, which are stored in pre-assigned, deterministic locations in the shared memory. The PPBL notifies the host processor of each message address location which allows the processor to directly read the data out of the shared memory and to notify the PPBL when the processor completed message access.
The present interface apparatus may include a plurality of individual serial receivers to permit the simultaneous receipt and translation of signal data from a plurality of different CSDB, and presenting this translated data to the host computer. This autonomous interface to multiple CSDB busses dramatically reduces the complexity and throughput requirements of the host computer itself, thereby reducing overall system cost.
These and other objects, features, and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying Drawing.